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ADMISSION ENQUIRY - 2024
DIGITAL ELECTRONICS
GANPAT UNIVERSITY |
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FACULTY OF ENGINEERING & TECHNOLOGY |
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Programme |
Bachelor of Technology |
Branch/Spec. |
Computer Engineering, Information Technology, Computer Engineering (Artificial Intelligence) |
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III |
Version |
2.0.0.0 |
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Effective from Academic Year |
2023-24 |
Effective for the Batch admitted in |
July 2022 |
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Course Code |
2CEIT301 |
Course Name |
Digital Electronics |
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Teaching Scheme |
Examination Scheme (Marks) |
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(Per week) |
Lecture (DT) |
Practical (Lab.) |
Total |
CE |
SEE |
Total |
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L |
TU |
P |
TW |
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Credit |
3 |
0 |
1 |
- |
4 |
Theory |
40 |
60 |
100 |
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Hours |
3 |
0 |
2 |
- |
5 |
Practical |
30 |
20 |
50 |
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Pre-requisites |
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NA |
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Course Outcomes |
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On successful completion of the course, the students will be able to: |
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CO1 |
understand basic digital components for circuit design. |
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CO2 |
explain various number systems and their conversion used in digital components. |
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CO3 |
design and optimize combinational and sequential circuits. |
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CO4 |
design basic electronics circuits for various applications using digital components. |
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Theory Syllabus |
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Unit |
Content |
Hrs. |
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1 |
Binary Systems: Digital Computer & Systems, Binary Numbers, Number Base conversions, Different Number systems & their relations, Complements, Binary codes, Binary storage & registers. |
06 |
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2 |
Digital Integrated Circuits: RTL, DTL circuits, I2L Logic, TTL, ECL, MOS & CMOS circuits & their characteristics, source current & sink current. |
04 |
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3 |
Boolean Algebra & Logic Gates: Basic definitions, Axiomatic definition of Boolean Algebra, Basic Theorems & Properties, Boolean functions, Canonical & Standard forms, Logic operations, Digital Logic gates & Logic families. |
05 |
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4 |
Simplification of Boolean Functions: Map method, Two, Three, Four, Five & Six variable maps, Products of Sum & Sum of Products simplification, NAND, NOR & Other two-level Implementations, Don't care conditions, Tabulation method. |
07 |
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5 |
Combinational Logic: Design Procedure, Address, Subtractors, Code Conversion, Analysis Procedure, Multilevel NAND & NOR circuits, Exclusive-OR & Equivalence functions. |
06 |
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6 |
Combinational Logic with MSI & LSI: Binary Parallel Adder, Decimal Adder, Magnitude Comparator, Decoders, Multiplexers, ROMs, PLAs, Introduction of PLDs, CPLDs and FPGA. |
07 |
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7 |
Sequential Logic: Latch, Flip Flops, difference between latch and flip flop, Triggering of Flip flops, Analysis of clocked sequential circuits, State reduction & assignment, Flip Flop Excitation tables, Design of Sequential circuits, Design of counters, Design using state equations. |
07 |
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8 |
Registers and Counters: Registers, Shift registers, Ripple Counters, Synchronous Counters, Memory. |
03 |
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Practical Content |
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Practical, assignments and tutorials are based on the syllabus. |
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Text Books |
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1 |
Digital Logic and Computer Design by Morris Mano, Pearson Publication. |
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Reference Books |
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1 |
Digital Electronics Circuits & Systems by V. K. Puri, McGraw Hill Education. |
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2 |
Digital Fundamentals by Floyd, Pearson Publication. |
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3 |
Modern Digital Electronic by Y R. P. Jain, McGraw Hill Education. |
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ICT/MOOCs Reference |
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1 |
https://nptel.ac.in/courses/117106086/ |
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2 |
https://nptel.ac.in/courses/108105132 |
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Mapping of CO with PO and PSO: |
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PO1 |
PO2 |
PO3 |
PO4 |
PO5 |
PO6 |
PO7 |
PO8 |
PO9 |
PO10 |
PO11 |
PO12 |
PSO1 |
PSO2 |
PSO3 |
|
CO1 |
3 |
2 |
3 |
2 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
2 |
2 |
2 |
0 |
CO2 |
3 |
3 |
3 |
3 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
2 |
3 |
3 |
0 |
CO3 |
3 |
3 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
1 |
0 |
2 |
3 |
2 |
0 |
CO4 |
3 |
3 |
3 |
3 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
2 |
3 |
3 |
0 |